Rockwell Automation Publication 5069-AP001A-EN-P - August 2020 73
Appendix A
Program Conversion Errors (PCE) Messages
Introduction Table 1 lists all of the messages that are generated with a PCE instruction. The
text is appended to the rung comments that have the PCE instruction. The
message text begins with asterisks (*) and the words “Generated by RSLogix
Project Migrator”, and ends with asterisks.
Table 1
lists the message identifiers, descriptions, and when they are logged.
Table 1 - PCE Messages
ID Text When logged
101
The address references a counter’s Update Accum (UA) bit field. This is not
supported in the Logix Designer application.
Each time a reference to a counter’s UA field is encountered (SLC only)
102
The address references a counter’s Overflow(OV) or Underflow(UN) field. This
has been translated but the translation needs to be validated.
Each time a reference to a counter’s OV or UN field is encountered
103
Warning: Status files do not exist in the Logix Designer application. GSV
instructions are used in the Logix Designer application to obtain controller
information where applicable. This translation must be validated.
Each time a reference to the S file is encountered
105 The address references an indirect file number. It was not translated. Each time an address reference with an indirect file number is encountered
107
The address reference may have an incorrect index. The translation needs to
be validated.
Each time suitable index into the array could not be determined
108
The BTR, BTW or MSG instruction has been translated. However, the translation
needs to be validated. These instructions have many parameters that cannot
be directly translated and require review.
Each time a BTR, BTW or MSG instruction is translated
109
PLC-5 and SLC s use 0.01 second and 1 second timebases. the Logix Designer
application uses a 0.001 second time base. The address references a ’s
Accumulator (ACC) field. The translation needs to be validated.
Each time a reference to a ’s ACC field was encountered
110
PLC-5 and SLC s use 0.01 second and 1 second timebases. the Logix Designer
application uses a 0.001 second time base. The address references a ’s Preset
(PRE) field. The translation needs to be validated.
Each time a reference to a ’s PRE field was encountered
113
Follow the <FBC or DDT> instruction with MOV and FAL instruction on parallel
branches to make sure the correct bits are being operated on.
Each FBC and DDT instruction
114
Although the PID instruction has been translated, the PID instruction has many
parameters that do not translate directly to the Logix Designer application. The
translation must be verified.
Each time a PID instruction is translated
115
16-bit parameters have been extended to 32-bit. Verify bit manipulation is
correct.
Each time BSL, BSR, BTD instruction is translated
116
The structure of FOR/NXT/BRK statements has changed in the Logix
architecture. In the PLC-5 processor, the FOR and NXT instruction enclosed a
section of code that was to be iterated multiple times, while the BRK
instruction provided a way to break out of the repeating code.
In the RSLogix architecture, the FOR instruction calls a given routine a specific
number of times, so a NXT instruction is not needed. The BRK instruction works
in a similar fashion as in the PLC-5 processor. Because this architecture
change is significant, you may need to restructure your logic.
Each time FOR/NXT/BRK instructions are encountered
117 AGA instruction not supported. Each time a AGA instruction is found
119 CIR/COR not supported. Each time a CIR or CIO instruction is found
120 Source and destination types differ When source and destination types differ in a COP instruction
121 DFA instruction not supported Each time a DFA instruction is found
122 ERI/ERO instruction not supported. Each time a ERI or ERO instruction is found
123 IDI/IDO instruction not supported. Each time a IDI or IDO instruction is found